Cadence Design Techniques not too long ago launched a silicon-proven IP for the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process.
The brand new multi-standard IP is focused for functions akin to knowledge middle, storage, synthetic intelligence/machine studying (AI/ML), and hyperscale computing. Supporting each DDR5 and LPDDR5 protocols makes the brand new IP a single-chip answer that can be utilized in merchandise with completely different DRAM necessities.
Block diagram of Cadence’s LPDDR PHY IP. Picture used courtesy of Cadence
DDR5, with its excessive knowledge charge, is anticipated to own as giant as 43% of the worldwide DRAM market share by 2024, in keeping with SK Hynix. One of many key methods that make the excessive knowledge charge of DDR5 a actuality is decision feedback equalization (DFE).
On this article, we’ll check out one other vital method, particularly the DDR calibration idea, that permits the optimum efficiency of this reminiscence interface.
We generally must make use of a number of reminiscence chips to extend a system’s reminiscence capability. In these instances, the wiring technique can have a big impression on the last word reminiscence efficiency. One possibility is the T-branch connection proven beneath.
A double-T structure for DDR format and routing. Picture courtesy of Altium
With this configuration, which is usually used with DDR2 chips, the CLK/command/tackle traces are routed to a central level after which distributed from that central node to completely different DRAM chips. This enables us to have matched hint size for the CLK/command/tackle traces when speaking with completely different reminiscence chips within the system.
Having virtually the identical propagation delay for the CLK/command/tackle alerts simplifies the design process. Nevertheless, a T-branch topology will increase the capacitive loading of those sign traces.
Another answer is the fly-by topology employed with DDR3 and newer generations of DDR expertise. The fly-by topology incorporates a daisy chain construction when routing clock, command, and tackle traces from the controller to the DRAM chips. That is depicted beneath.
Fly-by topology. Picture courtesy of Altium
Notice that the info (DQ) and strobe alerts (DQS) are related in a star configuration as within the case of a T-branch connection. With fly-by configuration, we will extra simply cope with the elevated capacitive load as a result of the arrival time of alerts at completely different DRAM chips is barely completely different.
Because the alerts encounter the enter capacitance of the DRAM chips at barely completely different instances, the general capacitive load seems as a distributed load to those alerts. Therefore, for a given system reminiscence capability, the capacitive loading is successfully lowered, and consequently, sign integrity and knowledge charge are improved.
The draw back to this system is that the management and tackle alerts which are daisy-chained expertise a bigger delay in comparison with the info and strobe alerts which have a shorter point-to-point connection. Moreover, the management and tackle alerts arrive at completely different DRAMs at completely different instances. At speeds higher than 1 GHz, these time skews could make it very difficult to satisfy the sign set-up/maintain time necessities.
To handle this situation, high-bandwidth reminiscence interfaces, akin to DDR4 and DDR5, make use of coaching modes to measure the time skew of PCB traces. Having the time skew, the controller can introduce an applicable delay to the info alerts pushed from the controller to the DRAMs in order that the info arrives with a well-understood timing relationship with respect to the command and tackle alerts.
Certainly one of these coaching modes is write leveling.
For a dependable write operation, the sting of the strobe sign (DQS) ought to be inside a predefined neighborhood of the clock edge. With fly-by topology, the clock sign that’s daisy-chained experiences a bigger delay in comparison with the strobe sign that has a shorter point-to-point connection. To align these two alerts, DDR3 and newer DDR generations supply the write leveling coaching mode.
On this mode, which occurs throughout machine initialization, the controller continually sends strobe alerts to a selected DRAM. When the DRAM receives the strobe sign, it samples the clock sign and returns its worth on the info bus again to the controller.
At the start of write leveling, the returned worth is zero as a result of the clock sign experiences a bigger delay. The controller will introduce an increasing number of delays to the DQS sign till the controller observes a transition from zero to at least one on the info bus. At this level, the controller will lock on this calibrated delay setting and use it for future write operations.
The controller will introduce this delay to the info and strobe alerts when performing write operations. This de-skew will make knowledge and management alerts arrive on the DRAM inputs with applicable timing. The next determine illustrates the write leveling coaching mode.
A timing diagram that depicts the earlier than and after results of write leveling. Picture courtesy of NXP
Notice that the skew between clock and DQS is just not the identical for the completely different DRAM chips. Therefore, write leveling ought to be carried out for every DRAM within the system.
Coaching Modes of DDR5
DDR5 helps a number of completely different coaching modes which have a big impression on its excessive knowledge charge functionality. Along with write leveling mentioned above, DDR5 features a new learn preamble coaching mode, command/tackle coaching mode, and chip choose coaching mode. DDR5 additionally has new performance to compensate for the unrivaled DQ-DQS receiver structure, additional enabling sooner knowledge charges.
The info patterns related to DDR5 learn coaching embody the default programmable serial sample, a easy clock sample, and a linear suggestions shift register (LFSR)- generated sample that can be utilized to have a extra sturdy timing margin whereas coping with the DDR5 excessive knowledge charges.