GUC Die-to-Die (D2D) Whole Resolution Opening the New Period of Flagship SoC

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GLOBAL UNICHIP CORP.  

11.17.2020

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International Unichip Corp. (GUC), the Superior ASIC Chief, disclosed at the moment that it has efficiently demonstrated the silicon-proven GLink (GUC multi-die interLink) interface utilizing TSMC 7nm course of and TSMC InFO_oS superior packaging know-how for AI, HPC and Networking functions to do multi-die integration for system scaling.

GLink over InFO_oS is adopted as a consequence of InFO_oS price effectivity for modular, scalable and high-yield multi-die ASICs. GLink over CoWoS is adopted by prospects utilizing multi-die ASICs with HBM reminiscences. GLink’s low space/energy overhead for top throughput interconnect permits environment friendly multi-die InFO_oS and CoWoS options as much as 2500mm2.

Error-free communication between dies with full duplex 0.7 Tbps site visitors per 1 mm of beachfront, consuming simply 0.25 pJ/bit (0.25W per 1 Tbps of full duplex site visitors) was demonstrated. Testing outcomes are absolutely correlated with pre-silicon simulations in all process-voltage-temperature corners. Early adopting prospects are supplied with detailed testing reviews.

GLink’s energy consumption is 6 to 10 instances decrease than different resolution utilizing ultra-short attain SerDes-based communication by bundle substrate. For each 10 Tbps of full duplex site visitors it consumes 15 to 20 W much less energy than different SerDes-based interface. GLink IP occupies twice much less silicon space and it helps each InFO_oS and CoWoS die integration platforms.

Subsequent era GLink IP supporting 1.three Tbps error-free full duplex site visitors per 1 mm of beachfront with the identical 0.25 pJ/bit energy consumption is already accessible utilizing TSMC 5nm course of. Following era of GLink supporting 2.7 Tbps/mm error-free full duplex site visitors with the identical 0.25 pJ/bit energy consumption utilizing TSMC 5nm and 3nm course of can be accessible throughout 2021. Such low energy/space and site visitors per beachfront effectivity makes GLink IPs good for AI, HPC and Networking functions.

SerDes-based chips devour fixed energy based on absolute worst case site visitors state of affairs. GLink-based chips devour energy based on precise site visitors and information sample. SerDes-based interfaces randomize information and devour fixed energy based on worst case information sample. They all the time devour the identical quantity of Watts even when site visitors is diminished and information just isn’t random. GLink parallel bus doesn’t randomize information, it consumes energy proportionally to precise information toggle price and even additional reduces the toggle price utilizing DBI. It permits our prospects to devour 15 to 20 instances much less energy in sensible use circumstances than in the event that they used SerDes-based hyperlinks.

“Having a full set of best-in-class and silicon confirmed HBM2E/three PHY/Controller, GLink, CoWoS and InFO_oS experience, bundle design, electrical and thermal simulations, DFT and manufacturing check underneath one GUC roof permits our ASIC prospects fast design cycle, quick convey up and manufacturing ramp up. Robust momentum of GLink adoption by our AI, HPC and Networking prospects helps our dedication to constructing huge IP portfolio and deepening GUC design experience specializing in superior packaging revolution” explains Dr. Ken Chen, president of GUC.

“We leveraged experience from 5 generations of our HBM PHYs and Controllers in an effort to outline a brand new class of excessive site visitors density, low energy, low latency, error-free GLink interfaces. We’re dedicated to maintain doubling GLink site visitors density yearly whereas holding the identical energy and latency. Ranging from 2021 we’re going to complement HBM3 and GLink with GLink-3D bringing order of magnitude increased site visitors density, order of magnitude decrease latency and plenty of instances decrease energy utilizing TSMC 3DFabric know-how” mentioned Igor Elkanovich, CTO of GUC.

Key highlights

  • Error-free, full duplex 0.7 Tbps site visitors per 1 mm of beachfront
  • 25 pJ/bit (i.e., 0.25W per 1 Tbps of full duplex site visitors)
  • Testing outcomes absolutely correlated with simulations in all PVT corners
  • PPA benefit over SerDes/Bundle Substrate
    • 6 to 10 instances decrease energy consumption
    • For each 10 Tbps of full duplex site visitors it consumes 15 to 20 W much less
    • Twice much less silicon space
  • GLink’s low space/energy overhead for top throughput interconnect permits environment friendly multi-die CoWoS and InFO_oS options as much as 2500 mm2

GLink Analysis board and InFO_oS Engineering Pattern

Learn more about GUC’s GLink IP with InFO/CoWoS Total Solution

For extra data, please contact your GUC gross sales consultant straight or electronic mail [email protected]

About GUC

GLOBAL UNICHIP CORP. (GUC) is the Superior ASIC Chief, who gives the semiconductor trade with main IC implementation and SoC manufacturing providers, utilizing superior course of and packaging know-how. Primarily based in Hsin-chu Taiwan, GUC has developed a worldwide status with a presence in China, Europe, Japan, Korea, and North America. GUC is publicly traded on the Taiwan Inventory Alternate underneath the image 3443. For extra data, go to www.guc-asic.com

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