Introduction to JTAG and the Check Entry Port (TAP)

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JTAG has turn out to be a typical in embedded methods, and it’s obtainable in practically each microcontroller and FPGA in the marketplace. It is named for the group which developed it: the Joint Check Motion Group.

For those who’ve programmed a microcontroller in the previous couple of years, there’s a powerful likelihood that you’ve got used JTAG or one of many associated requirements. So it’s price asking: What precisely is JTAG? How does it work? And what are you able to do with it?

 

What Is JTAG?

It was once the case that testing a board with many IO paths required one thing like a mattress of nails testbench. Nonetheless, as pin density elevated and as ball-grid-array (BGA) packaging turned extra prevalent, a brand new methodology of testing was required. An answer was wanted which examined {hardware} interconnects between a number of ICs.

And so, within the 1980s, boundary-scan was developed, and standardized in IEEE 1149.1-1990, IEEE Standard for Test Access Port and Boundary-Scan Architecture. This commonplace expertise turned recognized to builders and engineers as JTAG. 

 

JTAG Boundary Scan

The usual itself supplies the implementation of boundary scan: every IO pin on a tool is supplied with a small logic cell between the inner logic and the bodily pin, and all of those logic cells are related in order that they will shift knowledge in a single course across the chip. Pin values could be learn or written, to check performance.

As well as, it specifies a check entry port (TAP) which is a logic block answerable for executing checks and managing knowledge circulate alongside the boundary cells. The TAP, which is actually a state machine and a number of other shift registers, could be made to execute instructions, like knowledge load and knowledge learn. However the framework is normal sufficient that producers have freedom so as to add instructions and logic blocks which give issues like programming and debugging entry. 

 

Why Is JTAG Widespread?

So how did JTAG turn out to be synonymous with machine programming? Recall that any machine which has reminiscence could be programmed by, first, addressing a phrase and, second, writing knowledge to that deal with.

Early reminiscence units utilized asynchronous addressing, usually with out decoding, utilizing a matrix-like deal with scheme. Information is supplied by way of separate knowledge pins, one for every bit within the reminiscence phrase. Quickly, binary decoding for addresses decreased the required pin depend and allowed for bigger reminiscences, and later the appliance of serial protocols allowed a programmer to speak with the machine utilizing just a few pins, for reminiscences of any measurement.

Then, as JTAG’s flexibility allowed builders to implement customized logic, it, too, turned used for programming. The info pipeline which the JTAG TAP supplies is nicely suited to the duty of microcontroller and FPGA programming, and the standardization of the interface helped create uniformity throughout units (although, as we’ll see, there’s broad selection throughout implementations). 

Additional extensions of the usual, equivalent to ARM’s Serial Wire Debug (SWD), in addition to further IEEE 1149.x requirements, would increase the usual’s applicability and utility, permitting JTAG to turn out to be what we all know right now.

Although it’s a commonplace, IEEE 1149.1 leaves quite a bit to the developer. There aren’t any commonplace pinouts, no commonplace connectors, and just a few built-in instructions. Past the essential state machine, many options usually are not required to be compliant; even the boundary scan performance is non-obligatory. We’ll see extra of this selection within the articles to return. 

With that historical past lesson over, let’s transfer on to the usual itself.

 

The Check Entry Port (TAP)

Determine 1 exhibits the essential JTAG structure. 

 

Determine 1. JTAG structure schematic
 

Let’s work from the underside up. There are 4 required indicators within the JTAG commonplace, and one non-obligatory sign. All JTAG-compliant units should have:

  • Check knowledge enter (TDI) pins
  • Check knowledge output (TDO) pins
  • A check clock pin (TCK)
  • A test mode choose pin (TMS) for controlling the TAP state machine

The check reset pin (TRST), which forces the state machine into the reset state, is non-obligatory, as a result of the reset state can at all times be obtained by holding TMS low and clocking TCK 5 occasions. 

 

The TAP Controller

The check entry level (TAP) consists of the TAP controller, an instruction register, and a number of other check knowledge registers, along with some glue-logic. The TAP controller incorporates the testing state machine, and is answerable for deciphering the TCK and TMS indicators. The info enter pin is used for loading knowledge into the boundary cells between bodily pins and the IC core, and loading knowledge into the instruction register or one of many knowledge registers. The info output pin is used to learn knowledge from the boundary cells, or to learn knowledge from the instruction or knowledge registers. 

The TAP controller’s state machine is manipulated by the mode choose sign, TMS, which is clocked by TCK. There are solely two “paths” which the state machine takes, representing two totally different modes: instruction mode and knowledge mode. The mode is chosen by clocking in a TMS HIGH or TMS LOW bit. Then, when in a given mode, the state machine both progresses (TMS HIGH) or strikes towards the reset state (TMS LOW). We’ll take a look at the state machine intimately within the subsequent article. 

 

Find out how to Use JTAG

Working with JTAG sometimes works as follows:

  1. First, the instruction mode is chosen. One of many states throughout the instruction mode ‘path’ permits the person to clock in an instruction by way of TDI.
  2. Then the state machine progresses till it resets.
  3. For many directions, the following step is to pick the information mode. On this mode, knowledge is loaded by way of TDI and/or learn from TDO. The info paths for TDI and TDO can be configured in accordance with the instruction that has been clocked in.
  4. When the learn or write operation is full, the state machine once more progresses to the reset state. 

 

Check Directions and Information Registers

There are two knowledge registers and 4 directions which the JTAG commonplace requires in all units. One other six knowledge registers and 13 directions are additionally standardized, however not required.

The info registers required are:

  • BSR – “Boundary-scan register”, the primary register for passing knowledge to the boundary-scan cells
  • BYPASS – A single-bit pass-thru register, connecting TDI to TDO with out first passing by way of the boundary-scan cells

Distributors can implement different knowledge registers relying on their design wants, whether or not standardized or design-specific. The one directions the JTAG commonplace requires to be applied are:

  • EXTEST – Carry out an “exterior” boundary-scan check utilizing the boundary scan cells
  • SAMPLE and PRELOAD – Boundary scan whereas the machine is useful
  • BYPASS – Bypasses the boundary scan cells altogether

 

Widespread JTAG Directions

Different really useful directions embody:

  • IDCODE – Output an identification code saved in an identification knowledge register
  • CLAMP and HIGHZ – Used to isolate elements of the machine with out danger of injury. HIGHZ forces all logic outputs to high-impedance mode, whereas CLAMP forces logic outputs to explicit values, e.g. to make sure a tool doesn’t reply when different units are being examined
  • IC_RESET – Obligatory when a reset choice register is applied, permits for management of machine resets and energy
  • CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS – Obligatory when Check Mode Persistence (TMP) is applied by way of a TMP controller
  • INIT_SETUP, INIT_SETUP_CLAMP, and INIT_RUN – Advisable when a tool has programmable IO pins

Moreover, there are non-obligatory directions that are outlined in the usual however usually are not among the many required or really useful directions:

  • RUNBIST – Constructed-in system checks, managed internally
  • INTEST – Inner boundary-scan check
  • USERCODE – Person-programmable ID code is shifted out
  • ECIDCODE – Electronic chip identification code, an identifier for the silicon die itself

The directions are assigned binary codes, and could also be thought-about public (for the end-user/designer) or personal (for machine verification by the machine vendor). Most directions would not have necessities for the binary worth, which means it’s the alternative of the producer. One exception is the BYPASS instruction, which is {1,1,…,1}, i.e. all ones. The usual does require that every one doable instruction binary codes, whether or not legitimate or invalid, default to some well-defined habits. 

Most JTAG directions can broadly be described as connecting totally different knowledge registers to the TDI/TDO path. The BYPASS instruction connects TDI on to TDO by way of a 1-bit shift register, the IDCODE instruction connects the identification code register to TDO, the EXTEST, INTEST, SAMPLE, PRELOAD directions all join the boundary-scan register (BSR) knowledge register to TDI and TDO, and so forth. 

Now you would possibly ask, how are we presupposed to know what the instruction codes are?

As talked about, that is vendor-specific, however typically the JTAG interface can be wrapped in a “middleware” structure which not solely consists of the JTAG TAP, but additionally the interface and connections to the machine core, equivalent to FLASH reminiscence, or ROM reminiscence, or CPU registers. An instance of a middleware structure is Arm’s CoreSight structure, and extra significantly the Arm Debug Interface (ADI), which provides further construction to the JTAG TAP within the type of a debug port, entry ports, and machine sources. 

 

Conclusion

We now perceive broadly what JTAG is, and what it will probably do. We noticed the JTAG TAP (check entry port), and a number of other directions and knowledge registers.

There’s nonetheless lots of data to cowl, most vital being the TAP state machine, which is the subject of the following article. With an understanding of the state machine and TAP, we are able to start to maneuver past the JTAG commonplace, wanting on the Arm Debug Interface and explicit JTAG interfaces such because the Seggar J-Hyperlink and the Black Magic Probe.

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