The JTAG Check Entry Port (TAP) State Machine

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Within the first half to this sequence, we checked out JTAG, the ubiquitous microcontroller/FPGA/ASIC interface standard. However whereas we coated loads of floor concerning directions and registers, we nonetheless want to grasp how you can function the JTAG check entry port (TAP).

As talked about within the earlier article, the TAP is managed by a state machine, which has two paths relying on whether or not we’re loading an instruction, or studying/writing a knowledge register. On this half, we’re going to have a look at the state machine intimately, and we’ll even see some pseudocode for a easy JTAG interface.

 

The TAP State Machine

The state machine is proven, because it seems within the IEEE 1149.1-2013 commonplace, in Determine 1 under.

The state machine is straightforward, comprising two paths:

  • The information register (DR) path (proven in inexperienced), used for loading directions
  • The instruction register (IR) path (proven in blue), used for studying/writing knowledge from/to knowledge registers, together with the boundary scan register (BSR)

 

Determine 1. TAP state machine, as proven within the IEEE 1149.1-2013 commonplace. 

 

The state machine progresses on the check clock (TCK) edge, with the worth of the check mode choose (TMS) pin controlling the habits. 

Assuming the state machine begins at Check-Logic-Reset, we start by clocking a TMS = Zero to enter the Run-Check/Idle state, then clock a TMS = 1 to start deciding on a path. 

The roles of the totally different states are summarized briefly in Determine 2.

 

Determine 2. TAP state machine with state descriptions
 

To help in understanding these states, look once more on the JTAG system from the earlier article, Determine 3. 

 

Determine 3. JTAG structure

 

The TAP controller manages the state machine, and relying on the state chosen, the output MUX is switched.

The 2 paths are:

  • The instruction capture-shift path 
  • The knowledge capture-shift path

Notice how the boundary-scan register, which contains the boundary-scan cells across the IO pins, is without doubt one of the knowledge registers. Knowledge registers are shift-registers, and might be of arbitrary size.

 

Seize, Replace, and Shift States

Essentially the most ‘energetic’ states are the seize, shift, and replace states.

The seize state is probably essentially the most mysterious, performing totally different actions for the info path in comparison with the instruction path. Right here, seize means parallel loading knowledge right into a shift register, versus shifting the info in serial into the register. Shift means, as one would possibly count on, shifting knowledge into the shift register. Then, the replace stage latches the register, and the state machine can reset. 

Particularly, Seize-DR is the state the place, if wanted, check knowledge might be parallel-loaded into the shift-capture path of the present knowledge register. (The present knowledge register is about by the present instruction which was beforehand set.) Because of this knowledge is loaded, in parallel, into the info register chosen by the present instruction, versus shifting in. 

Seize-IR is used for fault isolation within the JTAG system, although the usual is imprecise about its goal. A hard and fast logic worth (which should finish in {…01}) is loaded in parallel into the instruction register shift-capture path. That is to say, the instruction register is parallel-loaded (as a substitute of shifting) with a hard and fast logic worth. 

The Shift-DR and Shift-IR states are the primary states for serial-loading knowledge into both knowledge registers or the instruction register. Whereas the state machine is in one among these states, TMS is held LOW, till the shifting operation is full. The Replace-DR and Replace-IR states latch the info into the registers, setting the info within the instruction register as the present instruction (and in doing so, setting the present knowledge register for the following cycle). 

Examples of manipulating the TAP state machine are sometimes given within the type of timing diagrams, however such diagrams are restricted of their capability to convey data, so the reader is referred to the JTAG commonplace itself for additional data, together with implementation ideas for numerous logic blocks. 

 

JTAG Interface Pseudocode

To flesh out the concepts above, on this part we are going to assemble some pseudocode that may management a JTAG interface (which might be so simple as a microcontroller improvement board). The code implements essentially the most primary capabilities with none error checking or particular dealing with of directions. A number of delays are included to handle timing, together with a brief delay to accommodate methods with multi-tasking that can’t assure timing. 

 

// Outline pins

JTAG_TMS = PA01

JTAG_TCK = PA02

JTAG_TDI = PA03

JTAG_TDO = PA04

// Create a string of 5 1’s, for forcing reset

tms_reset_str = {1,1,1,1,1}

// JTAG FUNCTIONS 

// Transmit a relentless string to the TAP, with out setting TDI or TDO

transmit_tms_str(tms_str)

{

    for i = 0 : len(tms_str)

    {

        set_pin(JTAG_TMS, tms_str[i])

        jtag_short_delay()

        set_pin(JTAG_TCK, HIGH)

        jtag_clock_delay() 

        set_pin(JTAG_TCK,LOW)

        jtag_clock_delay()

    }

}

shift_tdi_str(tdi_str)

{

    set_pin(JTAG_TMS, LOW) // Maintain TMS LOW whereas shifting<br />
<br />
   

    for i = 0 : len(tdi_str)

    {

        set_pin(JTAG_TDI,tdi_str[i])

        jtag_short_delay()

        set_pin(JTAG_TCK, HIGH)

        jtag_clock_delay()

        set_pin(JTAG_TCK, LOW)

        jtag_clock_delay()

    }

}

shift_tdo_str(size)

{

    // This operate returns the string shifted out from TDO

    set_pin(JTAG_TMS, LOW) // Maintain TMS LOW whereas shifting

    output_str = {}<br />
<br />
   

    for i = 0 : size

    {

        set_pin(JTAG_TCK, HIGH)

        jtag_short_delay()

        output_str += read_pin(JTAG_TDO)

        jtag_clock_delay()

        set_pin(JTAG_TCK, LOW)

        jtag_clock_delay()

    }

    return output_str

}

reset_jtag()

{

    transmit_tms_str(tms_reset_str)

}

load_jtag_instruction(instr)

{

    // Assuming we're in run-test/idle

    // Notice: No error checking, early exiting, or pausing is 

    // applied right here

    transmit_tms_str( {1,1,0,0} ) // Places us at Shift-IR state

    shift_tdi_str( instr ) // Shift within the instruction knowledge

    transmit_tms_str( {1,0,1,1,0} ) // Return to Run-Check/Idle

}

read_jtag_register(reg_length)

{

    // This operate reads the present knowledge register (set by most 

    // current instruction)

    // Assuming we're in run-test/idle

    // Notice: No error checking, early exiting, or pausing is  

    // applied right here

    transmit_tms_str( {1,0,0} ) // Places us at Shift-DR state

    reg_str = shift_tdo_str(reg_length) // Shift out register knowledge

    transmit_tms_str( {1,0,1,1,0} ) // Return to Run-Check/Idle

    return reg_str

}

 

You may see a sensible instance of JTAG interface programming when you browse the Black Magic Probe supply, available on Github here. (Particularly, take a look at the src/platforms/ listing and the src/embody/ listing). 

 

Conclusion

We’ve now seen a very powerful a part of the JTAG TAP, its state machine. The fabric coated within the first two elements of this sequence might be discovered within the IEEE 1149.1-2013 commonplace, together with many beneficial implementation hints and particulars.

From right here, we will probably be getting extra sensible, taking a look at numerous JTAG interfaces out there, speaking about pinouts and connectors typically used, and at last taking a more in-depth take a look at the Arm Debug Interface (ADI) for an instance of JTAG in observe. 

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