On this continuation of our sequence on transistor sizing in VLSI, we’ll go over the third and last mannequin in our sequence, the linear delay mannequin. Make sure you take a look at the earlier articles if you would like to be taught concerning the linear-RC delay model and the favored Elmore delay model.

The linear delay mannequin gives an easier method to mannequin the delay of huge RC distributed circuits in situations the place, as we noticed on the finish of the final article, the Elmore delay will get difficult or inaccurate.

On this article, we’ll learn to discover the optimum dimension of a transistor/logic gate current in a bigger circuit to supply the specified efficiency.

### What Does the Linear Delay Do?

Recall the earlier article, the place we used the Elmore delay to linearize an equal RC circuit mannequin into:

[t_{pd}=(p+gh)3RC]

the place p = parasitic delay.

[h=textit{fanout} =frac {textit{Input Capacitance}}{textit{Output Capacitance}}]

[g=textit{logical effort}]

With this expression, we will compute the optimum dimension of a multistage MOS circuit.

### What Is Logical Effort?

Logical effort is the ratio of the efficient enter capacitance of a gate to the enter capacitance of an inverter. Efficient capacitance on this sense implies the capacitance offered on the enter.

Take a look at the inverter proven within the determine beneath, the place PMOS is twice the unit dimension of NMOS to present equal rise/fall time.

**Determine 1. **Unit inverter circuit. All pictures tailored from CMOS VLSI Design (4th ed.)^{1} by Neil H.E. Weste and David Cash Harris

**Determine 1.**Unit inverter circuit. All pictures tailored from CMOS VLSI Design (4th ed.)

^{1}by Neil H.E. Weste and David Cash Harris

[textit{logical effort} (g) = frac {textit{effective capacitance}}{textit{effective capacitance of an inverter}} =frac{3C}{3C}=1]

For a 3-input NAND gate proven beneath, the capacitor offered on the enter B is (3C + 2C = 5C).

**Determine 2.** 3-input NAND gate

**Determine 2.**3-input NAND gate

Due to this fact the logical effort is

[textit{logical effort} (g) = frac {textit{effective capacitance}}{textit{effective capacitance of an inverter}} =frac{5C}{3C}=frac {5}{3}]

That is per the linearized delay derived within the earlier article as

(t_{pd}=(1+h)3RC) for Inverter

(t_{pd}=(5+ frac{5}{3}h)3RC) for NAND

A 3-input NOR gate proven within the determine beneath will give a logical effort of (frac {7}{3}) in case you apply the identical method.

**Determine 3. **3-Enter NOR gate

**Determine 3.**3-Enter NOR gate

This method can be utilized to calculate the logical efforts of different widespread logic gates as proven within the desk beneath.

*Desk 1. Logical effort of widespread gates*

Parasitic delay will be calculated utilizing the Elmore delay as described within the earlier articlehttps://www.allaboutcircuits.com/technical-articles/transistor-sizing-vlsi-design-linear-delay-model/ or by simulation. To briefly summarize the impact of the parasitic delay, take into account an N-input NAND gate and it Elmore delay equal worth is given within the determine beneath;

**Determine 4. **N-input NAND gate and RC equal circuit

**Determine 4.**N-input NAND gate and RC equal circuit

The Elmore delay is,

[t_{pd}=R(3nC)+ sum_{i=1}^{n-1}(frac{iR}{n})(nC)=left ( frac{n^2}{2}+frac {5}{2}n right )RC]

From the expression, the parasitic delay half is seen to extend quadratically with the quantity(n) of sequence transistors, which is why it’s advisable to cascade two smaller gates to kind a bigger one to scale back the enter parasitic delay of a gate. The implication of this may be additional noticed in a multistage logic community which is the sum of the delay of every stage within the path as proven within the multistage logic community proven within the determine beneath.

**Determine 5. **Multistage logic community

**Determine 5.**Multistage logic community

[D=sum{d_i} ; ;textit{where} ; ; d_i= g_ih_i+p_i]

[D=sum{g_ih_i} + sum{p_i}]

[D=sum{g_ih_i} + P ;; textit{where} ; g_ih_i = textit{stage effort}]

[F=prod {f_i}=prod {g_ih_i}=GH textit{(stage effort)}]

The trail electrical effort, H, is the ratio of the output capacitance of the trail to the enter capacitance of the trail.

[H = frac {textit{Capacitance at the output}}{textit{Capacitance at the input}}= prod{h_i}]

The trail effort F is the product of the stage effort of every stage. Because the purpose is to reach on the minimal delay worth every stage will contribute an equal quantity of stage effort to an n-stage crucial path. It’s required that every stage should have equal stage effort. Due to this fact for an N-stage community, the minimal stage effort is just;

(f_i=F^{frac{1}{N}})—–minimal stage effort

Due to this fact,

[sum{g_ih_i}=Nf_i]

Due to this fact the delay expression will be written as

[d = NF^{frac{1}{N}} +P]

To raised perceive how this idea is utilized in a real-world system, we’re going to take into account a useful unit required to drive 64 items of capacitance through an inverter. With the information of the logical effort, we will decide the optimum variety of levels to supply the minimal delay.

**Determine 6. **Comparability of various variety of levels of inverter buffers

**Determine 6.**Comparability of various variety of levels of inverter buffers

Word that the parasitic delay (p_i) for an inverter is 1, so for an N-stage inverter chain community, the overall parasitic delay P of the trail would be the sum of the parasitic delay of every inverter, which is N.

N = 1 | N = 2 | N = 3 | N = 4 |
---|---|---|---|

[textit{Recall},d =NF^{frac{1}{N}}+P] | [textit{Recall},d =NF^{frac{1}{N}}+P] | [textit{Recall},d =NF^{frac{1}{N}}+P] | [textit{Recall},d =NF^{frac{1}{N}}+P] |

[P=sum{p_i}=N =1] | [P=sum{p_i}=N =2] | [P=sum{p_i}=N =3] | [P=sum{p_i}=N =4] |

[F=GH = frac{64}{1} =64] | [F=GH = frac{64}{1} =64] | [F=GH = frac{64}{1} =64] | [F=GH = frac{64}{1} =64] |

[f_i =64^{frac{1}{1}}=64] | [f_i =64^{frac{1}{2}}=8] | [f_i =64^{frac{1}{3}}=4] | [f_i =64^{frac{1}{4}}=2.83] |

[d=(1)64^{frac{1}{1}}+1] |
[d=(2)64^{frac{1}{2}}+2] | [d=(3)64^{frac{1}{3}}+3] | [d=(4)64^{frac{1}{4}}+4] |

[d=65] | [d=18] | [d=15 (textit{lowest})] | [d=15.3] |

Because the 3-stage inverter design is the optimum design with the bottom delay, we will decide the dimensions of the inverter in every stage to present the optimum delay.

Since every stage effort (f_i = 4), then the primary inverter near the load capacitance is sized as,

[FI= frac{64}{C_{in}}, CIN=frac{64}{4}=16 ;textit{UNIT}]

The center inverter is derived as (FI= frac{16}{C_{in}}, CIN=frac{16}{4}=4 ;textit{UNIT})

Whereas the dimensions of the primary inverter on the enter is derived as,

[FI= frac{4}{C_{in}}, CIN=frac{4}{4}=1 ;textit{UNIT}]

The abstract of every stage is proven in determine 6 above. As will be noticed, a one-stage inverter community gives the most important delay, even-though the general dimension of the circuit will probably be minimal, the design will run extraordinarily gradual. Whereas the 3-stage design may have extra space, it gives the very best quantity of delay to the design, therefore making the system work in keeping with specification.

Thus far, we have now been capable of examine the varied delay fashions within the MOS circuit. Whereas these strategies are easy and fairly correct, they need to not function an entire substitute for CAD instruments in conditions the place accuracy is essential. Nonetheless, these strategies are appropriate to supply a fast and soiled method to develop insights into varied circuit topologies and demanding paths design.